[PLUG-ANNOUNCE] REMINDER: May PLUG Advanced Topics Meeting: Verilog Synthesis

[Michael Dexter]

Portland Linux/Unix Group Advanced Topics Meeting Announcement

What: Introduction to Verilog Synthesis
Where: Free Geek, 1731 SE 10th Avenue, Conference Room on the left
When: May 15, 2012 at 7pm
Who: Galen Seitz
Why: The pursuit of awesome, open technologies.

(This is an attempt a Google calendar compatibility. Is Why: Supported?)
:-)

This talk will introduce you to the joys and pitfalls of programmable
logic design using Verilog.  The focus will be on small designs that
could conceivably be undertaken by hobbyists.  While we could easily
spend weeks on the subject, we will try to cram the following into an
hour and a half or so:

* Overview of PALs, CPLDs, and FPGAs
* Why use programmable logic
* Verilog constructs for synthesis
* Synthesis workflow
* Simulation
* Guidelines for synthesis
* A demonstration

If your digital logic skills are a bit rusty, you may want to brush up
on your understanding of logic gates and D flip-flops ahead of time.
There are *many* sources of info on the net.  Here are couple that may
be useful:

<http://www.cs.oberlin.edu/~jdonalds/210/lecture08.html>
<http://www.cs.oberlin.edu/~jdonalds/210/lecture12.html>

Many will break for the Lucky Lab on Hawthorne afterwards.

See you there!

Michael Dexter
PLUG Volunteer