[PLUG] How to confirm OSS support before hardward purchase?

[Wil Cooley]

On Mon, 2006-09-11 at 10:18 -0700, Paul Heinlein wrote:

> In /proc/cpuinfo, the 'flags' section should report 'vmx' if ia32 VT 
> is enabled.

Aaaah, be careful though; CPU flags can lie.  I found out that hard way
recently when I upgraded my workstation.  I assumed that any full P4
w/EMT64 would naturally include Hyperthreading.  The mobo BIOS announced
that HT is enabled when it boots, but for the life of me, I couldn't get
an SMP kernel to recognize more than 1 CPU.

====================================================================
$ cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 15
model           : 4
model name      : Intel(R) Pentium(R) 4 CPU 2.66GHz
stepping        : 9
cpu MHz         : 2660.789
cache size      : 1024 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 5
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc pni monitor ds_cpl tm2 cid cx16 xtpr
bogomips        : 5327.30
====================================================================

Notice the 'ht'?  Surely it must support Hyperthreading!  Wrong.  The
2.66GHz don't.  I should've spent the $20 more for the 2.8GHz which does
support hyperthreading.

Interestingly, 'x86info' reports:

====================================================================
$ x86info
x86info v1.17.  Dave Jones 2001-2005
Feedback to <davej at redhat.com>.

Found 1 CPU
--------------------------------------------------------------------------
Found unknown cache descriptors: 64 81 91 96 112 124
Family: 15 Model: 4 Stepping: 9 Type: 0 Brand: 0
CPU Model: D (Foster)
Processor name string: Intel(R) Pentium(R) 4 CPU 2.66GHz

Feature flags:
 fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe sse3 monitor ds-cpl tm2 cntx-id cx16 xTPRExtended feature flags:
 xd em64t
Instruction trace cache:
        Size: 12K uOps  8-way associative.
L1 Data cache:
        Size: 16KB      Sectored, 8-way associative.
        line size=64 bytes.
L2 unified cache:
        Size: 1MB       Sectored, 8-way associative.
        line size=64 bytes.
Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries.
Found unknown cache descriptors: 64 81 91 96 112 124
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
Processor serial: 0000-0F49-0000-0000-0000-0000
The physical package supports 1 logical processors
====================================================================

On my 3GHz system at work x86info reports:
====================================================================
...
The physical package supports 2 logical processors
====================================================================

But I don't know if really knows or if it's just counting the ones it
finds--a test would a UP kernel or HT disabled would be required to
know.

Wil
-- 
Wil Cooley <wcooley at nakedape.cc>
Naked Ape Consulting, Ltd
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