[PLUG] help me understand this pin-level kernel-interface stuff
Galen Seitz
galens at seitzassoc.com
Wed Sep 24 12:20:55 UTC 2008
Russell Senior wrote:
> Hmm. Need help parsing this from lspci -vvv:
>
> 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
> Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA
> Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
> Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> Region 0: I/O ports at 6000 [size=8]
> Region 1: I/O ports at 6100 [size=256]
> Region 2: I/O ports at 6200 [size=64]
> Region 3: I/O ports at 1000 [size=32]
> Region 4: I/O ports at 9d00 [size=128]
> Region 5: I/O ports at 9c00 [size=64]
>
> In particular, what does the "size=foo" mean? The most likely seems
> to me to be the number of octets available starting at the indicated
> port address. But other interpretations are possible. Can anyone
> tell me with some confidence how to interpret the size number?
>
Size refers to the number of 8 bit locations decoded by the PCI device
beginning at the given I/O address. lspci is just telling you how
each Base Address Register(BAR) is programmed and the size of each
region. See section 6.2.5 of the PCI 2.2 spec. So for Region 0
above, the device will respond to I/O reads and writes at I/O address
0x00006000 through 0x00006007. Note that this does not necessarily
mean that you can use any size of i/o transaction you want. For
example, it could require the use of 8 bit or 16 bit i/o transactions
to properly access the registers.
The PCI spec is not freely available, but you might want to try
searching for it anyway.
--
Galen Seitz
Seitz & Associates
galens at seitzassoc.com
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